1. Field of the Invention
The present invention relates to a tri-state buffer circuit which is small in size but possesses a large current capacity.
2. Description of the Prior Art
Along with the increase in the degree of integration of integrated circuits due to advancement in recent years of semiconductor technology, power consumption in a chip is showing an increasing tendency. For this reason, reduction in the power consumption is being attempted lately by constructing integrated circuits by the use of CMOS circuits that have low power consumption.
Referring to FIG. 1, a prior example of the tri-state buffer circuit constructed with CMOS circuits is shown with reference numeral 10. The prior tri-state buffer circuit 10 has a switching unit 12 which generates switching signals (A) and (B) based on an input signal, a tri-state signal T, and an inverted tri-state signal T. The switching unit 12 consists of P-channel MOS transistors (referred to as "PMOS" hereafter) 14 and 16 that are connected in parallel, an N-channel MOS transistor (referred to as "NMOS" hereafter) 18 and PMOS 20 that are connected in parallel, and NMOS 22 and 24 that are connected in parallel. Further, the source terminals of PMOS 14 and 16 that are connected in parallel are connected to a voltage source Vcc, the source terminals of NMOS 22 and 24 that are connected in parallel are connected to the ground, and the respective pairs of transistors that are connected in parallel described above are connected in series. Moreover, the gate terminals of the PMOS 16 and the NMOS 22 are connected to an input terminal IN to which is input a signal to be buffered, the gate terminals of the PMOS 20 and the NMOS 24 are connected to a tri-state terminal T to which is input a tri-state signal T, and the gate terminals of the PMOS 14 and the NMOS 18 are connected to an inverted tri-state terminal T to which is input an inverted tri-state signal T.
The tri-state buffer circuit 10 further includes an output unit 26, and the output unit 26 is composed of a PMOS 28 that sends out a current from the voltage source Vcc to the output terminal OUT based on a switching signal (A) and an NMOS 30 that sends in a current from the output terminal OUT to the ground based on a switching signal (B). The source terminal of the PMOS 28 is connected to the voltage source Vcc, its drain terminal is connected to the output terminal OUT, its gate terminal is connected to the drain terminals of the PMOS 14 and 16 that are connected in parallel, and a switching signal (A) that is generated in the switching unit 12 is supplied there. Further, the source terminal of the NMOS 30 is connected to the ground, its drain terminal is connected to the output terminal OUT, its gate terminal is connected to the drain terminals of the NMOS 22 and 24, and a switching signal (B) that is generated in the switching unit 12 is supplied there.
In a buffer circuit constructed as above, when the tri-state signal T is on high level (referred to as "H" level hereafter) and the inverted tri-state signal T is on low level (referred to as "L" level hereafter), the PMOS 14 becomes on-state and the NMOS 18 becomes off-state without depending upon the level of the input signal, that is, regardless of "H" or "L" level of the input signal level, and the switching signal (A) becomes "H" level and the switching signal (B) becomes "L" level. Further, both of the PMOS 28 and the NMOS 30 of the output unit 26 are in off-state, and the output terminal OUT becomes high impedance (HZ) state. On the contrary, when the tri-state signal T is on "L" level and the inverted tri-state signal T is on "H" level, the PMOS 14 is in off-state, the NMOS 18 is in on-state, the PMOS 20 is in on-state, and the NMOS 24 is in off-state. Further, when the input signal is on "L" level, the PMOS 16 is in on-state, the NMOS 22 is in off-state. Then, both of the switching signals (A) and (B) become "H" level so that the PMOS 28 becomes off-state and the NMOS 30 becomes on-state, a current flows from, for instance, a load resistance that is connected to the output terminal OUT to the ground via the NMOS 30, and the output terminal OUT becomes "L" level. Moreover, when the input signal is on "H" level, the PMOS 16 becomes off-state, the NMOS 22 becomes on-state, and both of the switching signals (A) and (B) become "L" level, so that the PMOS 28 becomes on-state, the NMOS 30 becomes off-state. Then, a current flows in from the voltage source Vcc through the PMOS 28 to, for example, a load capacity that is connected to the output terminal OUT so that the output terminal OUT becomes "H" level. Namely, the system functions as a buffer circuit.
Therefore, it will be seen that a tri-state buffer circuit with a construction as above performs a logic operation as shown in Table 1.
TABLE 1 ______________________________________ T --T IN (A) (B) OUT ______________________________________ L H L H H L H L L H H L -- H L HZ ______________________________________
Now, in order to drive a large load by employing a buffer circuit with construction as above to, for instance, the line driver of a data bus line, it becomes necessary to increase the current driving capability of the MOS transistor in the output stage. Since, however, the current driving capability of a MOS transistor is ordinarily not high enough, the required increase in the current driving capability is arranged at present to be accomplished by increasing the gate width of the transistor. More precisely, in order to let the current be flowed through the PMOS 28 of the output unit 26 from the voltage source Vcc to the output terminal OUT be, for instance, about 55 mA (at an output voltage of 2.8 V), it is necessary to give an area of about 500 .mu.m.sup.2 for the gate of the MOS 28. Further, in order to let the current that is to be flowed in by the NMOS 30 from the output terminal OUT to the ground be about 30 mA (at an output voltage of 1.0 V), the gate area of the NMOS 30 has to be made to be about 250 .mu.m.sup.2. Therefore, to increase the current driving capability, it becomes necessary to set the occupying area of the transistor in the output stage to be considerably larger in comparison to the occupying area of other circuit elements. As a result, it has been an obstacle in raising the degree of integration of the tri-state buffer circuit.